Many programmable logic devices (PLDs) incorporate embedded speed sensitive architectures, e.g., blocks of random access memory (RAM) used as a specialized dedicated resource freeing programmable function generators to carry out other tasks. As with other semiconductor devices, these RAM blocks typically include a plurality of memory cells arranged by rows and columns to form a relatively dense array. Each row of memory cells connects to a word line that, when activated by the decoding of an address, accesses the bit cells of that row. Word line activation causes the data of each cell of the row to be passed to a pair of bit lines of the column in which the cell is located. A sense amplifier is then enabled at the appropriate time after the bit line voltages have stabilized to sample the voltage difference on the bit lines, and convey the sampled data to an output register or some other output. Sampling the bit lines too early, i.e., before the differential true/complement voltages are fully developed can result in an incorrect reading of the bit lines. Sampling the bit lines later than really needed can slow down RAM operation thereby reducing the performance of the block RAM and the overall device in which the RAM is embedded.
Although there are a number of technologies available, PLDs typically employ complementary metal oxide semiconductor technology (CMOS) to implement static RAM blocks in a PLD. Efforts to increase density and speed in the CMOS block RAMS have made the circuitry more vulnerable to manufacturing variations, power fluctuations, and operating environmental changes. For example, variations in the process used to produce the memory circuit, can cause the circuitry formed on one part of the device to have different operating characteristics from circuitry on another part of that same device. This creates problems when generating control signals that sequence and/or control the operation of a RAM block, such as the enable signals used to control the sense amplifiers discussed above. These process variations can cause the sense amplifiers in one RAM block to be enabled and sample the bit lines at the wrong time, causing faults in the memory read process and the production of bad data.
A common solution to adjust for such process variations is to incorporate a self timing circuit into the RAM block that generates control signals, such as the enable signal for the sense amplifier, thereby controlling the access to the RAM to occur at the right time. By placing the self timing circuit in the same geographic location on the device and using the same types of device structures as the block RAM itself is made from, the designer can be confident the self timing circuit will create the enable signal at the appropriate time. One typical self timing circuit design uses an inverter chain made from inverters tuned to have the same delay as the cross coupled inverters that make up the block RAM cells to generate the control signals. These self timing circuits can ameliorate problems created by process variations or variations resulting from operating conditions (e.g., temperature and/or power fluctuations). This and other typical prior art self-timed reference circuit solutions are disclosed in U.S. Pat. No. 6,212,117, U.S. Pat. No. 6,201,751, and U.S. Pat. No. 6,301,176 which are hereby incorporated by reference in their entireties.
One of the problems with these approaches is the self-timed delay path is not adjustable after the device is manufactured. Because the self-time delay circuit is not adjustable after manufacture, a large design margin must be incorporated into the design to increase manufacturing yield of devices that meet the design requirements. However, incorporating large design margins into the self-timed circuit design inhibits the speed and maximum performance that can be expected from the memory. This reduced memory performance in the block RAMS also reduces the overall performance of the PLD. The large design margin also makes it difficult or impossible to migrate the block RAM memory design to a different manufacturing process, different voltage supply level, or different speed-grade when trying to balance those desired features and obtain optimum yields in the manufacturing process.
Moreover, as the development of the silicon manufacturing process technology continues, feature sizes are shrinking rapidly. As a result of shrinking feature sizes, process variation becomes more pronounced, decreasing manufacturing yields. Likewise, parasitic capacitances become more significant, also reducing manufacturing yield. Moreover, it is increasingly difficult to track the reference path delay with the data path delay precisely across different manufacturing lots. To address these issues design margins can be increased, further sacrificing memory performance for design yield. Alternatively, design margins can be left unchanged in order to enhance performance, causing functional instability and yield loss.
Accordingly, an approach that eliminates these disadvantages is needed.